报 告 人：X. Sharon Hu（胡小波） 教授
工作单位：Department of Computer Science and Engineering at the University of Notre Dame, USA
X. Sharon Hu is a professor in the department of Computer Science and Engineering at the University of Notre Dame, USA. Her research interests include low-power system design, circuit and architecture design with emerging technologies, real-time embedded systems and hardware-software co-design. She has published more than 300 papers in these areas. Some of her recognitions include the Best Paper Award from the Design Automation Conference and from the International Symposium on Low Power Electronics and Design, and the NSF CAREER award. She has participated in several large industry and government sponsored center-level projects and is a theme leader in an NSF/SRC E2CDA project. She served as the General Chair and Program Chair of Design Automation Conference and is the Program Chair of 2019 IEEE Real-Time Systems Symposium. She also served as Associate Editor for IEEE Transactions on VLSI, ACM Transactions on Design Automation of Electronic Systems, etc. and is an Associate Editor of ACM Transactions on Cyber-Physical Systems. X. Sharon Hu is a Fellow of the IEEE.
Data transfer between a processor and memory is a major bottleneck in improving application-level performance. This is particularly the case for data intensive tasks such as some machine learning applications. In-memory computing, where certain data processing is performed in memory, could be an effective solution to address this bottleneck. Consequently, compact, low-power, fast and non-volatile in-memory computing is highly desirable. This talk presents a cross-layer effort of designing in-memory computing modules based on ferroelectric FETs, an emerging, non-volatile device. An FeFET is made by integrating a ferroelectric material layer in the gate stack of a MOSFET, and can behave as both a transistor and a non-volatile storage element. This unique property enables area efficient and low-power finely integrated logic and memory. Novel circuits/architectures based on FeFETs to accomplish computing in memory, content addressable memory and crossbar arrays will be elaborated. Application-level benefits, particularly for machine learning, in comparison with other alternative technologies will be discussed.